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Dr. Roberto Muscedere

Assistant Professor


519-253-3000 ext. 4798


Old Drama Building 22



General Information

I've received my Ph.D. (2003), M.A.Sc. (1999), and B.A.Sc. (1996) degrees from the University of Windsor, Ontario in Electrical and Computer Engineering. During most of this time I was also the lab manager for the Research Centre for Integrated Microsystems, formally VLSI Research Group. My duty was to design and maintain a reliable computing environment which enabled students and researchers to build various types of integrated circuits and electronic devices. This environment features industrial EDA tools from companies such as Cadence, Synopsys, Mentor Graphics, and Xilinx. I soon became the in-house experience on these design tools as I had the opportunity to learn most of their features while testing each of them for compatibility in the design environment. This experience allowed me to become involved with many other projects with other students and researchers. I became interested in different research areas as I worked on several projects related to them. One of these projects, in particular, was a new number system based on the Logarithmic Number System (LNS), known as the Double Base Number System (DBNS, later generalized to the Multi-Dimensional Logarithmic Number System, MDLNS) was developed by a post doctoral fellow while he was at the University of Windsor. Although primarily intended for cryptography applications, we had started looking at using DBNS for high-speed DSP. One of the issues with DBNS was that we could not easily move data encoded in binary into the DBNS domain. I began analyzing the problem and found a preliminary systematic method to do just this. This became the basis for my future doctoral work.

Research Areas

My Master's degree (1996-1999) was based on research to improve real-time product defect detection. This work was targeted to applications in which several Dalsa line-scan cameras are used to visually inspect a moving paper-like product for defects immediately after it has been manufactured. These cameras were connected to localized high performance computers (essentially home PCs) so that they could perform the video-processing. In the event a defect was found, that area of the product was marked as bad, or in a more severe case, the production was stopped entirely. The environment in which the product was manufactured was not environmentally adequate for the computers. PCs are not typically designed to handle the electrical noise and dust which are commonly found in manufacturing areas. In order to maintain the video bit rates, differential parallel data transfers are used to connect the cameras to the PCs. Never the less these PCs would require constant maintenance and/or replacement and therefore slow down production. This project involved moving the heavy video processing load from the localized computers into the cameras themselves. The PCs were processing the load of many cameras (up to 16). If the processing were moved to the cameras themselves, they would only need to process data at the actual video rate. The PC-like performance wouldn't be needed as the work would be distributed in the cameras. PCs are basically general processors running non-real-time operating systems and for this application they require addition buffering data acquisition boards to handle the incoming real-time data. All of this equipment can be very expensive. It was determined that selecting high volume, common electronic components would be used in order to produce a reasonably inexpensive on-board camera processing system. The final system was designed to use both a Field Programmable Gate Array (FPGA), for real-time processing, and a Digital Signal Processor (DSP), for further, more elaborate processing. To reduce the need for expensive data acquisition boards with differential parallel inputs, we decided to look at more modern technologies for high speed data transmission in electrically noisy environments. Ethernet was one of the first options examined as it offered a networking topology, however, the speed was limits to 10Mbps and the bandwidth was not always guaranteed. Another option was a new emerging technology that offered network configurations, low-cost, high-speed serial transmission at 400Mbps with a guaranteed quality of service. This technology is known as Firewire or IEEE1394 and was suited perfectly for this application and was chosen to be the transmission medium for the cameras to the PCs. The processing system was designed, layed-out on three PCB boards so that it would connect directly to the existing cameras. Once built, the software for the PC was written along with the firmware of the on board controller and they were thoroughly tested. The design worked as intended and was able to process the data at real-time with a variety of inspection algorithms, while reducing the information into more manageable data and transmitting it to the host PC. This design was a test bed for other types of research, such as real-time fuzzy logic algorithms and camera self-syncing algorithms. Some aspects of this work have been adopted by Dalsa Inc. such as the on-board FPGA, real-time compression algorithms, firmware compression algorithms, and camera self-syncing algorithms.

For my Doctoral degree I worked on developing generalized methods to perform what are known as difficult operations in the MDLNS. Although my initial work was for DBNS with fixed parameters, my primary goal was to create a method to solve the Binary-to-MDLNS (low bit range, approximately 32) conversion problem with a generalized MDLNS (any number of digits, any set of bases, any range). My solution to the Binary-to-MDLNS conversion requires a new CAM (content addressable memory) structure, which I refer to as a Range Addressable Look-Up Table (RALUT), that basically acts as a non-linear look up table (LUT). By using this device we can easily realize the solution for Binary-to-MDLNS any number of digits, and any set of bases. Addition and subtraction are commonly known as difficult operations in LNS and MDLNS. The simple solution is to use LUTs to map all possible inputs to all possible outputs. However, this can create impractically large tables. In my Doctoral thesis I detailed a realizable method to solve the addition and subtraction problem for single-digit, double-base MDLNS. This method involves computing and optimizing smaller tables used in these operations.

Since my work was intended to be for generalized MDLNS, I developed software based on the methods in the Binary-to-MDLNS that would find an optimal base for a multi-digit, double-base MDLNS representation. This allows us to optimize our MDLNS representation for particular applications (e.g. DSP FIR filters). Using most of the components of my Doctoral thesis, I was able to redesign a previous design of an MDLNS 8 bank filter-bank for hearing instrument applications showing significant improvements in area, routing and power.

External Affiliations

  • Professional Engineers Ontario

Additional Links

Departmental CV

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