Complimentary Metal Oxide Semiconductor (CMOS) Processes
The CMOS Processes which are currently being used by the RCIM include:
CMOSP8: (0.8-micron)
CMC Microsystems offers access to DALSA Semiconductor's 0.8-micron CMOS
technology (CMOSP8) with three different process flavors: high-voltage (up to
300V), mid-voltage range (+/-20V), standard-voltage (2.7V to 5.5V).
DALSA Semiconductor’s high-voltage CMOS is integrated with standard baseline
CMOS and the combination provides excellent driving or actuating capabilities as
well as signal conditioning and processing capabilities. CMC Microsystems has
added this technology to its portfolio to support increased research and
technology development activities that explore heterogeneous microsystems and
target diverse application spaces. High-voltage electronics are often required
for driving flat display panels, automotive applications, actuating MEMS
devices, stimulating muscles in an implantable device, and manipulating
particles or cells in fluidics.
90nm CMOS
The new CMOS090 design platform is based on ST's latest 90nm CMOS process
technology, supplied through a partnership with CMP (Circuits Multi-Projets,
France). Designed as a modular process, it allows maximum flexibility in
combining multiple features. The 90nm design platform is intended for
System-on-Chip (SoC) and ASIC solutions that target wireless, low-power,
consumer, networking and hi-speed applications. Based on dual-damascene copper
technology, it allows 6 to 9 metal layers of interconnect and a library density
of more than 400,000 gates per mm2. This technology offers 65nm poly
length [90nm drawn, per CMP web site], dual Vt MOS transistors, dual
gate oxide, dedicated process flavors for high performance or low power,
dual-damascene copper for interconnect, low-k (k = 2.9) dielectric, 6 to 9 metal
layers for interconnect, 0.28um metalization pitch, analog/RF capabilities,
fully compatible with e-DRAM, and various power supplies (3.3V, 2.5V, 1.8V,
1.2V, 1V).
CMOSP13 (0.13-micron)
This technology, manufactured by IBM and supplied through collaboration with
CMC Microsystems
and MOSIS. It is an 8-layer metal structure with 1.2 V core and 2.5 V supply
voltages.
CMOSP18 (0.18-micron)
This technology, developed by TSMC and supplied through collaboration with
MOSIS, is a 0.18-micron, single poly, six metal, salicide CMOS process. The
recommended nominal supply voltages are 1.8 and 3.3 volts. This technology is
suitable for design in the following areas: analog, low power, RF, and full
custom digital. The minimum drawn gate length is
0.18 microns.
CMOSP35 (0.35-micron)
This technology, manufactured by TSMC and provided through
CMC Microsystems and TMSC, PMC-Sierra or MOSIS, is a 0.35-micron dual poly, triple metal,
polycide CMOS process. The recommended nominal supply voltage is 3.3 volts. The
technology is suitable for designs in the following areas: analog, low power, RF,
high-speed digital, DSP and synthesis. The minimum drawn gate length is 0.35
microns.
CMC Microsystems's fabrication service includes automatic substitution of "phantom" or
"black box" cells with the complete version of their layout.
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